The present invention generally relates to methods and devices for testing semiconductor memory devices, and more particularly to a semiconductor memory testing device and testing method which allows testing of a semiconductor memory device to be performed in a swap mode, that is, in a mode in which X and Y addresses of the semiconductor memory device are interchanged.
In semiconductor memory devices such as a ROM (Read Only Memory) or a RAM (Random Access Memory), storage cells are arranged in an X-Y matrix form, and a desired storage cell is selected by specifying the X-address and Y-address. However, when the capacity of a semiconductor memory device of the above type is increased as in an LSI (Large Scale Integrated) circuit, the probability of hardware errors being introduced during the manufacturing stage into the storage cells of one or more bits, becomes high.
Conventionally, a method was proposed in which redundancy bits are provided to replace the defective bits having hardware errors, to decrease the percentage of the defective bits within the memory device. Another method proposed is a method in which error correcting codes are used to compensate for the defective bits within the system. Hence, defects in some bits of the memory device does not make the whole memory device (chip) defective. However, there is a problem. The problem is that, the memory device which is ready for use is tested before it is built into a system, but when a defective bit exists in the memory device, the margin characteristic of the memory device cannot be determined, and the testing of the memory device is interrupted.
In order to overcome the above described problems, still another method was proposed which stores the address of the defective bit into another memory (fail memory) device, so that when access is made to the defective bit, this access is prohibited by the output signal supplied from the above fail memory device, and masking of the memory device is performed during the operational testing. That is, if a defective bit exists at a certain address of a RAM device, for example, an information to indicate that the bit at this certain address is defective, is written-into a fail memory device at the same address location as that of the above certain address. Hence, upon operational testing of this RAM device, access is made to the fail memory device together with the RAM device, and, according to the information stored in the fail memory device, prohibits the operational testing of the defective bit within the RAM device is prohibited. Accordingly, the RAM device can be tested as if no defective bits existed even when defective bits exist in that RAM device, and, the RAM device tested can be treated as being fully operational, when there are no other defective parts within the RAM device.
The operational testing is also performed under a swap mode in which the X and Y addresses of the memory device are interchanged, in contrast to a normal mode in which access to the bits of the memory device are made in the order the address is specified. This testing under the swap mode is sometimes necessary, since some of the characteristics of a memory device depend on the address patterns. For example, there often are cases in which the defective bits are concentrated in certain columns (Y-side) or rows (X-side), within the memory device. In this case, the whereabouts of the defects can be easily found, when the X and Y addresses are interchanged and scanning is performed along the column or row having concentrated defective bits therein. Furthermore, there are many types of testing systems, mainly, galloping system, walking system, and like, and the address swapping is required to perform these types of tests.
Generally, when the addresses of the bits in the memory device are specified by a 12-bit signal (A.sub.0 .about.A.sub.11), the lower six bits (A.sub.0 .about.A.sub.5) of the above 12-bit signal generated by an address pattern generator is selected as the X-address, and the higher six bits (A.sub.6 .about.A.sub.11) as the Y-address. Therefore, when a defective bit exists at the X-address (A.sub.0 .about.A.sub.5) "010000" and Y-address (A.sub.6 .about.A.sub.11) "001000" in a normal mode, for example, the address of the defective bit in the swap mode in this case becomes "010000" for the XX-address (A.sub.6 .about.A.sub.11) "001000" for the YY-address (A.sub.0 .about.A.sub.5) since the address pattern generator maintains the same output as that upon normal mode, where XX and YY respectively designate the X and Y addresses in the swap mode. However, this address changeover is conventionally only performed for the memory device (usually a RAM device) and not for the fail memory device. Accordingly, the address upon normal mode is always set in the fail memory device, that is, "010000" for the X-address (A.sub.0 .about.A.sub.5) and "001000" for the Y-address, (A.sub.6 .about.A.sub.11) in the case of normal mode. But upon swap mode, when XX-address is "010000" and YY-address is "001000", the address in the fail memory device is set as being "001000" for the X-address and "010000" for the Y-address. This result does not correspond to the original address of the defective bit in the memory device, and hence the defective bit cannot be masked.
Therefore, in the conventional method, for example, the information stored in the fail memory device upon normal mode is erased and new information is stored into the fail memory device upon swap mode, to enable the masking of the defective bits. However, this operation of storing information into the fail memory device twice, complicates the testing method, and suffers disadvantages in that the required operation time is increased.